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Professor Hani H. Saleh is a Professor of Computer and Communications Engineering at Khalifa University, where he has advanced research and education since 2012. He currently serves as Deputy Director of the Khalifa University Center for Intelligent Computing, Networks and Sensing (KU-ICONS), established in 2026.
His research focuses on AI accelerators, ASIC and system-on-chip (SoC) design, edge computing, and Internet of Things (IoT) systems. He develops intelligent, energy-efficient hardware that brings AI closer to where data is generated, enabling faster, lower-power, and more secure applications in wearable healthcare, smart sensing, mobile vision, and autonomous edge devices.
A co-founder of the Khalifa University Research Center and a co-founder and theme lead at the System-on-Chip Research Center, Professor Saleh has led projects on wearable blood-glucose monitoring SoCs, mobile-surveillance SoCs, AI accelerators for edge devices, and low-power IoT platforms. His expertise spans digital ASIC design, computer architecture, RTL and physical design, embedded systems, in-memory computing, hardware security, and low-power VLSI design.
Before joining Khalifa University, he gained 19 years of semiconductor-industry experience at Apple, Intel, AMD, Qualcomm, Synopsys, Fujitsu, and Motorola Australia, contributing to microprocessors, DSP cores, graphics hardware, and widely used design IP. He has also supervised 13 PhD and 9 MSc graduates, helping develop the next generation of hardware and AI researchers.
Professor Saleh has authored more than 60 journal publications, six books, and nine book chapters. His innovation portfolio includes 12 granted US patents and five additional published patent applications in wearable health, computer vision, energy management, AI acceleration, and secure hardware.
Professor Saleh welcomes motivated students and researchers interested in building the intelligent, efficient, and trustworthy hardware that will power future AI and IoT systems.
Artificial Intelligence (AI) engines have been integrated into a myriad of applications, whether they run in data centers or on edge/end-node devices. Most contemporary AI applications use the cloud to execute computationally intensive and power-demanding deep learning algorithms. Moving the processing from the cloud to edge devices reduces data transfers and latency, improves security, and enables scalability. The huge computational requirements of deep learning neural networks (DNN) deem it necessary to achieve challenging tradeoffs among energy, latency, and accuracy, at every application level. This project will utilize alternative numbering systems and fused primitives to create DNN architectures with low latency, low energy, and high accuracy for AI implementation. Optimization at the algorithm and architecture level will enable the proposed architectures to attain target power and performance, moreover, optimized digital circuit primitives for functions that accelerate AI engines in FPGAs and ASICs will be developed, verified, and demonstrated in FPGA prototypes.
This project aims to achieve power-efficient and scalable AI architectures through the following
approaches.
RNS for AI
As in every digital application, the number representation scheme utilized in realizing AI architectures
directly impacts the accuracy, speed, area, and energy dissipation. It affects the way the hardware
implements all algorithmic operations and influences the complexity and utilization of the PE, the
required memory space, and the bandwidth required for memory access. In this project, RNS will be
used to perform tensor operations, such as direct sum, and vector product, as well as the comparisons needed
for deep learning AI applications, targeting the exploitation of its inherent parallelism, dynamic range
flexibility, power efficiency, and high-speed properties.
