To address the high demand for CMOS scaling and meet the beyond Moore challenge, novel structures and new materials are being introduced for the silicon industry. It is critical for nanoscale devices to employ novel channel materials to improve device performance and enable new functionality. Therefore, Ge is viable due to its higher hole and electron mobility compared to Si along with its strong absorber in the near-infrared light spectrum. This allow for monolithic fabrication of photodetectors and Si-CMOS receiver circuits. However, heteroepitaxial growth of high-quality films on silicon is challenging due to the 4.2% lattice mismatch with Ge. The goal of this project is to deposit a Ge layer with low surface roughness and threading dislocation density values at low temperature. And then followed by the fabrication of electronic and photonic devices based on this, along with integration with III-V and 2D materials (graphene) to explore new devices and architectures.