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  • Books, Journals and Conferences
  • Inventions & Patents
Books, Journals and Conferences

Books:

 

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Refereed Journals

 

2020

2019

2018

 

 

Refereed Conferences

Inventions & Patents
Tunable Non-Volatile Analog Resistive Memory and Its Application in AI: presented in 2020 IEEE 63rd International Midwest Symposium on Circuits and Systems (MWSCAS) by Dr. Heba Abunahla

This paper presents a novel analog resistive random-access memory (RRAM), named NeuroMem, which consists of Au/GO/Au. The device’s resistance can be tuned to any value within its R OFF to R ON range with high precision. The analog characteristic of NeuroMem mimics the memorization behavior of the brain, which makes it great asset for artificial neural network applications. In this work, NeuroMem-based crossbars are fabricated to hold the synaptic weights needed to perform Iris classification. The weight values are mapped to conductance states within NeuroMem R OFF to R ON range, and then written accurately on the actual devices. Unlike other RRAM-based hardware with limited conductance states, in this work no quantization is needed which enables efficient in memory-computing without scarifying accuracy. Furthermore, NeuroNem device has been demonstrated in crossbars on flexible polymer substrate using standard photolithography process, which facilitates producing low cost flexible electronics. This work opens up great insights towards realizing RRAM-based computing at the edge.

View full paper here: https://ieeexplore.ieee.org/document/9184484 

A 28GHz, Asymmetrical, Modified Doherty Power Amplifier, in 22nm FDSOI CMOS: presented in 2020 IEEE International Symposium on Circuits and Systems (ISCAS) by Nourhan Elsayed

A 28GHz, Modified Doherty Power Amplifier (MDPA) was implemented in 22nm FDSOI CMOS technology from GF. The MDPA adopts an asymmetrical topology utilizing two cascode CMOS amplifiers as the main (Class-A) and auxiliary (Class-C). This allows a supply voltage of 2.5V and consequently higher output power. The use of a main Class-A amplifier is conducive to a higher linearity (IIP3). The integrated design implements the main and auxiliary amplifier, along with the matching and transmission line networks on chip. The fabricated amplifier occupies an area of 1.2mm 2 , exhibits 12 dBm saturated output power, a peak power gain of 10dB, 16% peak power-added efficiency (PAE) and 12.5% at 6-dB back-off. The measured IIP3 is 20dBm.

 View full paper and presentation here: https://ieeexplore-ieee-org.libconnect.ku.ac.ae/document/9180851

ASIC Implementation of a Pre-Trained Neural Network for ECG Feature Extraction: Presented in 2020 IEEE International Symposium on Circuits and Systems (ISCAS) by Huruy Tesfai

The electrocardiogram signal (ECG), a record of electrical activity of the cardiac muscle, has been used in diagnosing many cardiopathies. Wearable devices equipped with readout sensors and circuits can be used to record and process weak ECG signals. In this paper, a pre-trained neural network was implemented for detecting the QRS feature of an ECG signal, which is crucial for auto-diagnostic of various cardiopathies. To take advantage of the fast evolution of artificial intelligence and its ability to find non-linear relationships, neural network based feature extraction of ECG signals for wearable devices was explored and tested using ASIC implementation flow. Firstly, a high-level simulation was carried out in MATLAB and verified with test data obtained from PhysioNET database. Recurrent neural network (RNN) MLP was created and trained using the data obtained from PhysioNET database. A high-level performance evaluation was carried out using the same network for P and T wave extraction. The weight and bias matrices obtained from the high-level trained network in MATLAB were used in the design of the hardware. An accuracy of 96.55% was achieved in the hardware implementation of the network.

View paper and presentation: https://ieeexplore-ieee-org.libconnect.ku.ac.ae/document/9180703/metrics#metrics

Ratioed Logic Comparator Based Digital LDO Regulator in 22nm FDSOI: presented in 2020 IEEE International Symposium on Circuits and Systems (ISCAS) by Dr. Dima Kilani

This paper presents a fast and an efficient digital LDO (DLDO) regulator utilizing a clock-less ratioed logic comparator (RLC). In addition to eliminating the clock, the proposed RLC-DLDO removes the shift registers used in the conventional DLDO. It achieves a transient speed improvement in the ns range and a quiescent current reduction by 9X over the conventional DLDO design that targets μA load current. The RLC-DLDO has an input voltage range between 0.8V and 0.6V and generates an output voltage range between 0.7V to 0.5V for load current between 10μA and 500μA. The design is implemented in 22nm FDSOI and occupies an active area of 0.0171mm2. The simulation results show that the peak efficiency is 99.9% and the load transient response time is 5ns at VL=0.5V.

View full paper and presentation here: https://ieeexplore-ieee-org.libconnect.ku.ac.ae/document/9181174