How 3D chip stacking may be the answer to smaller phones
We all want faster, smaller and more energy-efficient smartphones. Unfortunately, physics is getting in the way.
Moore’s Law, which states that the number of transistors on an integrated circuit doubles approximately every two years, is no longer held to be true. Tried and true methods for shrinking integrated circuits have nearly reached their economical implementation limit.
So scientists and engineers are working to find a way of pushing past that obstacle to deliver the next generation of circuit design.
One possible way of scaling up the performance of integrated circuits is 3D chip stacking.
Conventionally, the focus has been on simply shrinking the size of conventional 2D chips, to pack as much as possible into a single layer.
The 3D chip stacking builds on those efforts, by thinning these chips and stacking them on top of each other to produce high-speed and multifunctional systems.
These multilayered chips can incorporate vertical interconnects, transmitting data and power up and down the chip stack.
This not only increases the communication bandwidth between the chips in the stack, but also means the communication links between the various parts can be shorter. Shorter links means less delay and therefore better performance -and less power drain. A properly designed 3D stacked system can use as much as 70 per cent less power than a conventional chip.
But while this area of research has been gaining momentum over the past decade, with significant research from market leaders like Intel, much needs to be done to ensure that these far more complex chips function as seamlessly as needed.
In-depth exploration and testing must be done to learn how the close proximity of so many transistors, in three dimensions, affects the functionality of the chip in terms of its electrical, thermal and mechanical properties.
It is already known that the 3D design changes the stresses within the device. The thinned-down circuits do not behave in the same way, which can affect the transport of the electrons. And the stack design can get hot, too.
These factors can add up to create problems with the signals, voltage, material properties, device behaviour and material integrity, among other things.
The Masdar Institute has embarked on research that seeks to establish design and manufacturing guidelines for integrating electronics with photonic (eg. laser) circuits, and to characterise how thinning and stacking of the chips could potentially affect the behaviour of electrons and photons in a complex stacked system.
The major goal of this undertaking – which includes 12 individual projects – is to explore and illustrate the low-power features of 3D integrated microelectronics in a variety of computing, communication, storage and sensing design contexts.
My focus will be on the impact of stacking on the electronic circuits and their yield.
It is our hope that the sum of these projects will be a clearer idea of how to manage multifunctional, diverse integration of the chips, avoid thermal hotspots, and improve overall functionality in terms of power and speed.
We also hope to address the need for new computer-aided chip design algorithms that take account of the heating challenges.
And these projects will provide unique, functional and crucial hands-on experience for the professionals in the UAE’s vibrant semiconductor industry.
It should help Abu Dhabi develop indigenous know-how in 3D chipmaking – an area that will soon be the crux of our rapidly evolving high-tech world.
Dr. Irfan Saadat is a professor of microsystems engineering at the Masdar Institute of Science and Technology