Category Name > Advanced Technology & Security
This course is a hands-on introduction to ASIC design using Synopsys ASIC design tools flow. The attendees will be introduced to digital circuits timing for both combinational and sequential logic synthesis. They will be taught how
Who Should Attend
They will be taught how to perform synthesis, evaluate time, floorplan, place 7 route, and chip finishing their ASIC design.
ECE Engineers or anybody with basic ECE knowledge who are interested to learn ASIC Design Basics using industry standard Synopsys ASIC design tools.
- ASIC Flow & Digital Circuit ASIC Timing
- Synthesis & Static Timing Analysis (STA)
- Full day Lab about Synthesis and STA using Synopsys Design Compiler & Primetime tools
- Floorplanning, Clock Tree Synthesis, Place and Route, and Chip Finishing Parasitic Extraction, Timing closure, LVS & DRC
- Full day lab about Floorplanning to GDSII using the IC Compiler tool from Synopsys
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