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A Hands-on Introduction to ASIC Design Training

A Hands-on Introduction to ASIC Design Training

Course Date

Duration is 5 days

Course Description

This course is a hands-on introduction to ASIC design using Synopsys ASIC design tools flow. The attendees will be introduced to digital circuits timing for both combinational and sequential logic synthesis. They will be taught how perform synthesis, evaluate time, floor-plan, place 7 route and chip finishing their ASIC design.

Learning Outcomes: 

ASIC Flow & Digital Circuit ASIC Timing.  Synthesis & Static Timing Analysis (STA). Full day Lab about Synthesis and STA using Synopsys Design Compiler & PrimeTime tools.  Floorplaning, Clock Tree Synthesis, Place and Route and Chip Finishing. Parasitic Extraction, Timing closure, LVS & DRC. Full Day lab about Floorplaning to GDSII using IC Compiler tool from Synopsys.

Course Outline:

Day 1:  ASIC Flow & Digital Circuit ASIC Timing.

Day 2: Synthesis & Static Timing Analysis (STA).

Day3: Full day Lab about Synthesis and STA using Synopsys Design Compiler & PrimeTime tools.

Day4: Floorplaning, Clock Tree Synthesis, Place and Route and Chip FinishingParasitic Extraction, Timing closure, LVS & DRC. Day5:  Full Day lab about Floorplaning to GDSII using IC Compiler tool from Synopsys

Resources:

Synopsys ASIC Design Toll set, GF Foundries 65nm Process

Targeted Audience:

ECE Engineers or anybody with basic ECE knowledge who are interested to learn ASIC Design Basics using industry standard Synopsys ASIC design tools

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